The present invention is directed to a method for phase matching between a data signal and a clock signal.
European Patent Application No. 0 419 896 discloses a method wherein a number of phase clock signals exhibiting a same offset relative to one another are derived from a clock signal. A data signal and the phase clock signals are supplied to a data edge recognition means. A distribution signal is outputted from the data edge recognition means.
The distribution signal contains information about positions of edges of the data signal with reference to the individual phase clock signals. A calculating and outputting a delay value from the distribution signal is calculated in and output from a control means. A phase position is matched between the data signal and the clock signal in a data synchronization means. The matching being based on a criterion of a delay value supplied to the data synchronization means.
Data whose phase position is not defined and that also has jitter, pulse distortion and frequency offset must often be processed in transmission systems. A clock can have a jitter and a frequency offset when it derives from a different source. The incoming data is generated and synchronized to a predetermined clock.
It is an object of the present invention to improve the known phase; matching circuit such that an independent locating of a momentarily larger sampling range is established and, moreover, the jitter compatibility is enhanced.
This object is inventively achieved in accordance with the invention in a method in which a number of phase clock signals exhibiting a same offset relative to one another are derived from a clock signal. A data signal and the phase clock signals are supplied to a data edge recognition means. A distribution signal is determined over a measuring time span equal to a number of cycles of the data signal, the distribution signal containing information about positions of edges of the data signal with reference to the individual phase clock signals. The distribution signal is output from the data edge recognition means. A delay value is calculated and output from said distribution signal in a control means. The calculating and outputting comprising the steps of: addressing a tabularly stored allocation with the distribution signal; based on a criterion of the distribution signal, determining from the tabularly stored allocation a largest interconnected area of the data signal in which no transitions were registered; and outputting the allocated delay value. A phase position is matched between the data signal and the clock signal in a data synchronization means, the matching being based on a criterion of a delay value supplied to the data synchronization means.
By addressing the table with the distribution of the registered data edges, an independent and dependable recognition of not only whether and in what direction the delay value must be modified but also an jitter compatibility that is larger and, thus, better for the clocking of the data signal than the jitter compatibility to which the phase matching has momentarily engaged is established from the allocation stored in the table. The control of the phase matching can ensue with a bit repetition rate that is considerably reduced compared to the bit repetition rate of the data signal. The measuring time span within which transitions of the data signal can be detected is prescribable, particularly to a number of cycles of the data signal, wherewith the phase matching is independent of the content of the data signal. Alternatively, the number of data transitions can be prescribed in order to determine the distribution. Compared to the traditional phase matching of the present invention, the phase matching exhibits an enhanced jitter compatibility. The phase matching circuit of the application can be completely integrated and avoids circuit areas that are operated with a higher bit repetition rate than that of the clock signal.
In an embodiment, in a control means, the most recently determined delay value is stored and supplied to the table as additional addressing. This measure yields an addressing of the table dependent on the most recently identified delay value.
In an embodiment, in a control means, the most recently identified delay value is stored and a distribution signal shifted by the delay value is supplied to the table as addressing. This measure yields a compensation of the most recently identified delay value and, thus, a considerable reduction in the number of entries in the table.
In an embodiment, number of data signals are established to which a data edge recognition means as well as a data synchronization means are respectively allocated and which share the control means. Upon utilization of the perception in accord wherewith the control with a bit repetition rate that is substantially reduced compared to the bit repetition rate of the data signal can ensue, this measure yields a reduction of the percentage outlay for each data input.
In an embodiment, the control is respectively cyclically allocated to one of a number of data signals, whereby the time span for a data signal in which the control is not allocated to it forms a measuring time span. This measure yields a simple determination of the measuring time span.
In an embodiment the matching of the phase position between data signal and system clock signal for a respective measuring cycle is limited to an offset between two neighboring phase clock signals. This measure avoids instabilities.